Conventionally, there is proposed a semiconductor package having a semiconductor chip embedded therein. For example, the semiconductor package includes a first insulating layer sealing a target circuit surface (i.e. a surface on which a circuit is formed) and a side surface of a semiconductor chip, a first wiring layer formed (layered) on the first insulating layer and electrically connected to an electrode pad of the semiconductor chip, and other insulating layers and wiring layers formed on the first wiring layer.
The semiconductor package may be manufactured by the following steps. First, the first insulating layer is formed by arranging a semiconductor chip on a support member and sealing the target circuit surface and the side surface of the semiconductor chip. Then, a via hole, which exposes an electrode pad of the semiconductor chip, is formed in the first insulating layer. Then, a wiring layer, which is electrically connected to the electrode pad of the semiconductor chip interposed by way of the via hole, is formed on the first insulating layer. Then, for example, one or more other insulating layers and wiring layers are formed on the first wiring layer. Then, by removing the support member, the manufacturing of the semiconductor package is completed.    Patent Document 1: Japanese Laid-Open Patent Publication No. 2008-306071
However, the above-described semiconductor package has a structure in which the semiconductor chip is embedded only in the first insulating layer on a first side of the semiconductor package (with respect to the thickness direction) and only has a layered body including the insulating layer and the wiring layer on a second side of the semiconductor package (with respect to the thickness direction) without having the semiconductor chip embedded therein. This structure may lead to a problem of warping of the semiconductor package.
More specifically, in a case where the main component of the semiconductor chip is silicon, the thermal expansion coefficient of the semiconductor chip is approximately 3.4 ppm/° C., and the Young's modulus of the semiconductor chip is 200 GPa. Meanwhile, in a case where an epoxy type resin is the main component of the first insulating layer or the other insulating layer, the thermal expansion coefficient of the first insulating layer or the other insulating layer is approximately 8-150 ppm/° C. and the Young's modulus of the first insulating layer or the other insulating layer is approximately 0.03-13 GPa. Due to the different values of the physical properties (thermal expansion coefficient, Young's modulus) of the semiconductor package, the side of the semiconductor package having the semiconductor chip embedded in the first insulating layer (i.e. the first side of the semiconductor package) is resistant to deformation due to thermal stress or the like whereas the side of the semiconductor chip having no semiconductor chip embedded (i.e. the second side of the semiconductor package) tends to easily deform due to thermal stress or the like.
As a result, warping of the semiconductor package occurs at room temperature of, for example, approximately 20-30° C. (in this case, the semiconductor package tends to project toward the first side of the semiconductor package), and warping of the semiconductor chip occurs at a high temperature of, for example, approximately 200-300° C., (in this case, the semiconductor chip tends to become recessed toward the first side of the semiconductor package).
Because the semiconductor chip and layers such as the first insulating layer and the first wiring layer are formed on the substrate member having high rigidity according to the above-described steps for manufacturing the semiconductor package, warping hardly occurs before the removal of the support member. However, the removal of the support member causes loss of balance (unevenness) in the values of the physical properties (e.g., thermal expansion coefficient, Young's modulus) of the semiconductor package. This leads to warping of the semiconductor package.